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Application Note
LEDS
The LEDs provide feedback to the user about the status of the
IOVDD
AN-1006
10k0 10k0
Cypress USB microcontroller.
R3
R4
3V3DD
1 A0
U1
VCC
8
1
2
J2
2 A1
3 A2
4 GND
WP
SCL
SDA
7
6
5
3
SCL
SDA
24AA256-I/ST
IOVDD
3V3DD
5V0DD
Figure 23. EEPROM Schematic
TARGET BOARD POWER SWITCH
2
A
Y
4
D4
The USBi is capable of supplying power to the target board after
U4
RED DIFFUSED
the Cypress USB microcontroller has finished its boot up process.
TO U3
IOVDD
2
A
IOVDD
FXLP34P5X
3V3DD
4
Y
U5
FXLP34P5X
3V3DD
R10
475R
The USB_PWR_ON signal connects to the base of Q2 and turns
on both transistors when driven high.
This circuit also enables a software-controlled target reset from
SigmaStudio.
2
4
A
Y
U6
5V0DD
3 E
C
4
C 2
5V0DD_USB
FXLP34P5X
Figure 22. LEDs Schematic
FZT705TA
R12
100k
B 1
Q1
Table 1. LED Functions
E
Reference
Designator
D1
Color
Yellow
Functionality
I 2 C mode is active
USB_PWR_ON
R13
1k50
10k0
1
B
C 3
2
Q2
MMBT3904LT1G
D2
D3
D4
Blue
Yellow
Red
GPIO LED, for firmware debug purposes
SPI mode is active
5 V power being is supplied over the USB bus
R14
EEPROM
The EEPROM is an important system element that identifies
the board to the host PC and stores the firmware for the
Cypress USB Interface. The EEPROM is programmed during
manufacturing via the J2 connector.
Figure 24. Target Power Switch Schematic
TARGET BOARD PROGRAMMING HEADER
To properly boot the Cypress USB microcontroller from the
EEPROM, it is necessary to remove all other devices from the
I 2 C bus. The ADG721BRMZ analog switch remains open,
isolating the I 2 C bus from the target, until the boot process has
completed.
5V0DD_USB
ADG721BRMZ
U2-A
ADG721BRMZ
J1
SCL
USB_PWR_ON
S1 D1
IN1
CTRL SDA
USB_PWR_ON
U2-B
S2 D2
CTRL
IN2
CLATCH2
COUT
CCLK
CLATCH1
CLATCH4
1
3
5
7
9
11
13
2
4
6
8
10
12
14
CLATCH3
USB_CLK
BRD_RESET
CDATA
CLATCH5
2X5 CUSTOM RIBBON
3V3DD
C2
0.10uF
LOCAL FOR ADG721
Figure 25. Target Board Programming Header Schematic
Rev. A | Page 9 of 16
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